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IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)
t RC
ADDRESS
t OH
t AA
t OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
BUSY OUT
2654 drw 05
t BDD
(3,4)
Timing Waveform of Read Cycle No. 2, Either Side (5)
t ACE
CE
OE
DATA OUT
t AOE
t LZ (1)
(4)
t HZ (2)
VALID DATA
t HZ (2)
I CC
CURRENT
t PU
t LZ (1)
50%
t PD
(4)
50%
I SS
2654 drw 06
NOTES:
1. Timing depends on which signal is aserted last, OE or CE .
2. Timing depends on which signal is deaserted first, OE or CE .
3. t BDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, t AOE, t ACE, t AA, or t BDD.
5. R/ W = V IH , CE = V IL , and OE = V IL , and the address is valid prior to other coincidental with CE transition LOW.
7
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IDT70125L35JG
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